MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2246

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
37.3.5 Configuration of PWM
There is a hard-wired connection between PWM block and high-speed ADC block. This
wire is for PWM block to trigger the high-speed ADC to start the sampling. When the user
case is to drive a linear image scanner sensor, it is suggested to generate the sensor driving
signals by the operation clock, and use another PWM instance to generate the trigger signal.
It is required that the trigger pulse is active high and the duration is longer than one operation
clock cycle. The user can control time of the trigger pulse to control the sampling point of
ADC.
37.3.6 Configuration of High-speed ADC
There are two working mode which can be chosen, single mode and loop mode. For loop
mode, the high-speed ADC block enters into the status to wait for another trigger pulse once
the current sequence is finished. The number of samples and sequences can be configured.
There are up to eight channels, the user can choose one of the eight channels by configuring
the register. Also, the delay cycles between the trigger pulse and the time to start sampling
can be controlled by configuring register. Note that there are also two AHB clock cycles
and two operation clock cycles delay that are required to be added. The sample precision,
endian and whether to do half-word-swap can also be configured. There are three trigger
modes which can be selected as mentioned above. When hsadc_run bit is set, all these
settings take effect. The user can change these parameters when the ADC is working on the
current sequence and will take effect when hsadc_run bit is set again. When DMA get the
dma_req toggled, it will read out the sample data by APBH bus. It is also possible that the
ARM CPU reads the sample data through the APBH bus in some special user cases. When
one sequence is finished, all the sample data will be flushed out to the external memory. If
it is not an integer number of word, the unfilled bits will be left empty. There are some
read-only registers which contain necessary information for debugging, such as the current
state, the state machines inside the block, and sample number captured and sequence number
finished, and so on. If DCDC converter works to provide supply voltage, in order to attenuate
the impact of DCDC noise on HSADC performance, it is recommended to set the sampling
rate of HSADC to 1.5 Msps and set the register HW_POWER_ANACLKCTRL(0x80044160)
as 0x84000626. But, there would be some initial delay time (less than 0.67 us) between
HSADC starting conversion and 'start' command coming from software trigger or PWM
trigger. If the initial delay time is not desired, it is recommended to set the register
HW_POWER_ANACLKCTRL(0x80044160) as 0x84000426 and use PWM trigger mode.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2246
Freescale Semiconductor, Inc.