MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1732

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
The interrupt lines are tied directly to the bits of Control Register 1. Clearing these bits
through software removes the interrupt request.
27.2.2 I
The I
modes: DMA mode, PIO mode and PIO Queue mode. The discussion of the I
in the following subsections is written from the perspective of DMA mode. The descriptions
of how to use the other two modes and their similarities and difference from DMA mode
will be included in a later section.
In DMA mode, one DMA command chain can only contain one data-transfer command
besides address-transfer command(s). If it’s desired to transfer data to/from two different
system memory buffers, two dma transfer should be used.
The I
1732
Data Engine
Complete
Bus Free
Read Queue
Threshold
Write Queue
Threshold
SOURCE
• A START condition is defined as a high-to-low transition on the data line while the
• After this has been transmitted by the master, the bus is considered busy.
• The next byte of data transmitted after the start condition contains the address of the
I2C_SCL line is held high.
slave in the first seven bits, and the eighth bit tells whether the Master is receiving data
from the slave or transmitting data to the slave.
2
2
C block can be programmed and driven by the SoC using one of three internal interface
C interface operates as shown in
2
C Bus Protocol
DATA_ENGINE_CMPLT_IRQ
BUS_FREE_IRQ
RD_QUEUE_IRQ
WR_QUEUE_IRQ
Bit Name
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
This bit is set whenever the DMA interface state machine completes a
transaction and resets its run bit. This is useful for PIO mode transmit
transactions that are not mediated by the DMA and therefore cannot use
the DMA command completion interrupt. This bit is still set for master com-
pletions when the DMA is used, but can be ignored in that case.
When bus mastership is lost during the I
comes busy running services for another master. This interrupt is set
whenever a stop command is detected so the master transaction can attempt
a retry.
This interrupt is set whenever the read FIFO has filled up equal to or greater
than the programmed threshold level.
This interrupt is set whenever the write FIFO has drained down equal to or
less than the programmed threshold level.
Description
Figure 27-2
and
Figure
27-3.
2
C arbitration phase, the bus be-
Freescale Semiconductor, Inc.
2
C protocol