MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 347

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or SDRAM)
from the associated peripheral. Each peripheral has a target PADDR value that it expects
to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE
transfer uses the BUFFER_ADDRESS word in the command structure to point to the
beginning byte to write data from the peripheral.
DMA_READ operations copy data bytes to the APB peripheral from the system memory.
The DMA engine contains a shared byte aligner that aligns bytes from system memory to
or from the peripherals. Peripherals always assume little-endian-aligned data arrives or
departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS
word in the command structure to point to the DMA data buffer to be read by the
DMA_READ command.
The NO_DMA_XFER command is used to write PIO words to a device without performing
any DMA data byte transfers. This command is useful in such applications as activating
the NAND devices CHECKSTATUS operation. The check status command in the NAND
peripheral reads a status byte from the NAND device, performs an XOR and MASK against
an expected value supplied as part of the PIO transfer. Once the read check completes (see
NAND Read Status Polling
result in the peripheral is that its PSENSE line is driven by the results of the comparison.
The sense flip-flop is only updated by CHECKSTATUS for the device that is executed. At
some future point, the chain contains a DMA command structure with the fourth and final
command value, that is, the DMA_SENSE command.
As each DMA command completes, it triggers the DMA to load the next DMA command
structure in the chain. The normal flow list of DMA commands is found by following the
NEXTCMD_ADDR pointer in the DMA command structure. The DMA_SENSE command
uses the DMA buffer pointer word of the command structure to point to an alternate DMA
command structure chain or list. The DMA_SENSE command examines the sense line of
the associated peripheral. If the sense line is false, then the DMA follows the standard list
found whose next command is found from the pointer in the NEXTCMD_ADDR word of
the command structure. If the sense line is true, then the DMA follows the alternate list
whose next command is found from the pointer in the DMA Buffer Pointer word of the
DMA_SENSE command structure (see
bit, so that both pointers must be valid when the DMA comes to a sense command.
Freescale Semiconductor, Inc.
DMA COMMAND
11
DMA_SENSE. Perform any requested PIO word transfers, then perform a conditional branch to the next
chained device. Follow the NEXTCMD_ADDR pointer if the peripheral sense is false. Follow the BUFFER_AD-
DRESS as a chain pointer if the peripheral sense line is true. This command becomes a no-operation for
any channel other than a GPMI channel.
USAGE
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Example), the NO_DMA_XFER command completes. The
Figure
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
6-2). The sense command ignores the CHAIN
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