MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 109

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

See
1.3.20 SPDIF Transmitter
The device includes a Sony-Phillips Digital Interface Format (SPDIF) transmitter. It includes
independent sample-rate conversion hardware so that the A/D, D/A and SPDIF can run
simultaneously. The SPDIF has a dedicated DMA channel. The SPDIF has its own clock
divider from the PLL.
See
1.3.21 Dual Serial Audio Interfaces
The i.MX28 SOC includes two Serial Audio Interfaces (SAIF), each with three stereo pairs.
The pin multiplexing scheme for i.MX28 allows a stereo transmitter and a stereo receiver
to be connected to external devices, either D/A and A/D converters or to a host processor,
such as a cell phone or BlueTooth controller.
See
1.3.22 Rotary Decoder
An automatic rotary decoder function is integrated into the chip. Two digital inputs are
monitored to determine which is leading and by how much. In addition, the hardware
automatically determines the period for rotary inputs.
See
Freescale Semiconductor, Inc.
• The final stage of the PXP operation is the rotator which can perform flips and 90, 180
• The PXP supports scaling down up to 4:1 in single-pass mode. This is useful for scaling
8 × 8 or 16 ×16 block. The overlays are fetched into the internal S1 buffer. Alpha
blending is performed on the S0 and S1 buffers to generate the blended output into the
internal S3 buffer. Other operations such as BITBLT and color-keying can also be
performed at this stage.
and 270 rotations. The rotator operates on the 8 × 8 or 16 ×16 pixel blocks in the S3
buffer to maximize external memory fetch efficiency. It writes 8 × 8 or 16 ×16 blocks
to the external memory in this final stage.
720p decoded content to a QVGA display. The PXP can also be used to further scale
down images using a multi-pass approach which is enabled by the ability of the PXP
to write YUV output.
Pixel Pipeling (PXP) Overview
FlexCAN Introduction
Serial Audio Interface (SAIF) Overview
Timers and Rotary Decoder (TIMROT) Overview
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
for more information.
for more information on the PXP.
for more information.
for more information.
Chapter 1 Product Overview
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