MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1074

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

EMI AHB and AXI Interface
if an exclusive write fails its exclusivity check. The master that has lost exclusivity must
determine whether to restart the sequence by requesting another exclusive read or to write
the data to the memory regardless through a non-exclusive write.
14.4.8.1 Initiating an Exclusive Access Request
Exclusivity is enabled by issuing a read command to memory with the axi_ARLOCK signal
driven to ‘b01.
14.4.8.2 Verifying the Request
The AXI specification dictates restrictions for exclusive access requests. After being accepted
in the port, an exclusive read request will be checked against these requirements. If any of
these conditions are violated, the command will be passed to the core logic as a non-exclusive
read. These restrictions are:
In addition, the AXI specification states that exclusive accesses can not be cacheable.
However, since the EMI does not support cacheable commands, this bit is ignored and any
cacheable exclusive access requests will be processed as non-cacheable exclusive accesses.
14.4.8.3 Validity of an Exclusive Request
The exclusive access will be considered valid from the point that the entry is created in the
buffer until an activity occurs to invalidate it. These activities cause the “valid” bit of the
exclusive access buffer entry to be cleared:
Note: The EMI assumes that a single master will only communicate with a single port.
Therefore, a command to another port, with the same AXI ID (axi_AWID or axi_AWID)
will not violate the exclusivity of another port’s exclusive region simply based on ID match.
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• The address must be aligned to the total byte count. (Byte Count = (axi_ARLEN + 1)
• The byte count must be a power-of-two, and less than 128 bytes.
• The same source ID issues a write command for the same starting addressing of the
• Any other source ID, from that port or another port, writes to any memory address in
x 2^axi_ARSIZE)
same length and beat size.
that memory span.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.