MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 809

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Address:
Re-
9.4.54 PINCTRL Bank 1 Data Output Enable Register
The PINCTRL Bank 1 Output Enable Register controls the output enable signal for all pins
in bank 1 that are configured for GPIO mode.
HW_PINCTRL_DOE1: 0xb10
HW_PINCTRL_DOE1_SET: 0xb14
HW_PINCTRL_DOE1_CLR: 0xb18
HW_PINCTRL_DOE1_TOG: 0xb1C
For pins in bank 1 that are configured as GPIOs, a 1 in this register will enable the
corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin,
and a 0 in this register will disable the corresponding driver.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
RSRVD1
RSRVD1
0
0
31 29
Field
28 0
DOE
Field
31 0
DOE
30
30
0
0
29
29
0
0
(HW_PINCTRL_DOE1)
HW_PINCTRL_DOE0
HW_PINCTRL_DOE1
28
28
0
0
Empty Description.
Each bit in this register corresponds to one of the 29 pins in bank 0. Setting a bit in this register to one allows
the chip to drive the corresponding pin in GPIO mode.
Each bit in this register corresponds to one of the 32 pins in bank 1. Setting a bit in this register to one allows
the chip to drive the corresponding pin in GPIO mode.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
HW_PINCTRL_DOE0 field descriptions
HW_PINCTRL_DOE1 field descriptions
0
0
22
22
0
0
8001_8000h base + B00h offset = 8001_8B00h
8001_8000h base + B10h offset = 8001_8B10h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
DOE
15
15
0
0
Description
Description
DOE
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
Chapter 9 Pin Control and GPIO (PinCtrl)
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
809
0
0
0
0

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