MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1714

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1714
EVT_OFFSET_
EVT_OFFSET_
EVT_PERIOD_
EVT_PERIOD_
PIN_PERIOD_
ONE_SHOT
RESTART
RSRVD3
RSRVD4
ENABLE
Field
ENA
RST
ENA
RST
ENA
9
8
7
6
5
4
3
2
1
0
Resets the timer to zero. This has no effect on the counter enable. If the counter is enabled while the
command is triggered, the timer is reset to zero and starts counting from there.
Command bit: When set, all other bits are ignored during a write.
Reserved bits. Write as 0.
Enable external pin frc_evt_period assertion on period event when set.
Reserved bits. Write as 0.
Reset timer on periodical event. When set (1) the timer is reset to zero (wraps around) when the period
setting is reached (causing an periodical event). If cleared the counter will increment continuously until it
wraps around.
Should be set 1 for normal operation.
Enable periodical event. When set (1) a period event interrupt can be generated (EIR(TS_TIMER)) and the
external pin frc_evt_period is asserted when the timer wraps around according to the periodic setting
ATIME_EVT_PERIOD.
The timer period value should be set before.
Reset timer on offset event. When set (1) together with the EVT_OFFSET_ENA the timer is reset to zero
when the offset setting is reached (causing an offset event).
Enable one-shot offset event. When set (1) an offset-event interrupt can be generated (EIR(TS_TIMER)).
The bit is cleared when the offset event has been reached so no further event is created until the bit is set
again.
The timer offset value should be set before.
Avoid timer wrap around. If set, the timer stops at maximum. An overflow interrupt is caused (if enabled)
when the maximum is reached.
When cleared (default) the timer operates continuously.
When set (1) the timer starts incrementing. When (0) the timer stops at the current value
HW_ENET_MAC_ATIME_CTRL field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.