MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2012

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
31.7.35 Endpoint Setup Status Register
endpoint setup status
Address:
Re-
31.7.36 Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME)
This register is used in device mode only.
endpoint prime request
2012
set
Bit
W
ENDPTSETUPSTAT
R
31
0
Field
RSVD
30
31 8
Field
0
7 0
29
0
HW_USBCTRL_ENDPTSETUPSTAT
01ACh
(HW_USBCTRL_ENDPTSETUPSTAT)
28
0
Controller mode is defaulted to the proper mode for host only and device only implementations. For those
designs that contain both host & device capability, the controller will default to an idle state and will need to
be initialized to the desired operating mode after reset. For combination host/device controllers, this register
can only be written once after reset. If it is necessary to switch modes, software must reset the controller
by writing to the RESET bit in the USBCMD register before reprogramming this register.
0x0
0x2
0x3
27
0
HW_USBCTRL_USBMODE field descriptions (continued)
Reserved.
Setup Endpoint Status.
For every setup transaction that is received, a corresponding bit in this register is set to 1. Software must
clear or acknowledge the setup transfer by writing a 1 to a respective bit after it has read the setup data
from Queue head. The response to a setup packet as in the order of operations and total response time
is crucial to limit bus time outs while the setup lock out mechanism is engaged.
This register is only used in device mode.
26
0
HW_USBCTRL_ENDPTSETUPSTAT field descriptions
IDLE — IDLE.
DEVICE — DEVICE.
HOST — HOST.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
22
0
21
0
RSVD
20
0
19
0
18
8008_0000h base + 1ACh offset = 8008_
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
ENDPTSETUPSTAT
0
6
0
5
0
4
3
0
0
2
0
1
0
0