MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1503

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Each timer has an UPDATE bit that controls whether the free-running counter is loaded at
the same time the fixed-count register is written from the CPU. The output of each timer's
source select has a polarity control that allows the timer to operate on either edge.
Table 23-1
When generating a periodic timer interrupt using the RELOAD bit, the user must compute
proper fixed-count value (count_value) based on clock speeds and clock divider settings.
Note that, in this case, the actual value written to the FIXED_COUNT register field should
be count_value – 1. For one-shot interrupts (RELOAD bit not set), the value written should
be count_value.
Any timer interrupt can be programmed as an FIQ or as a regular IRQ. See
(ICOLL) Overview
For proper detection of the input source signal, it should be much slower than the pre-scaled
APBX clock (not greater than one-third the frequency of the pre-scaled APBX clock).
Selecting the ALWAYS tick causes the timer to decrement continuously at the rate
established by the pre-scaled APBX clock. The NEVER TICK selection causes the timer
to stall. Setting the fixed-count to 0xFFFFFFFF and setting the RELOAD bit causes the
timer to operate continuously with a 4,294,967,296 count.
The state of the 32-bit free-running count can be read by the CPU for each timer.
23.2.2 Match count mode
In this mode, the timer consists of a 32-bit match count value and a 32-bit free-running
count value. This mode is enabled once MATCH MODE of Register TIMERx Control
and Status Register (x = 0-3) is written to 1. At the same time, the free-running count
Freescale Semiconductor, Inc.
UPDATE
0
0
1
1
RELOAD
lists the timer state machine transitions.
0
1
0
1
PIO writes to the fixed-count bit field have no effect on the running count.
The value written to the fixed count is used to reload the running count the next time it reaches 0.
When the fixed count has been written with a value of 0 and the running count reaches 0, it continuously
copies the fixed count value to the running count. Therefore, writing a non-zero value to the fixed
count register kicks off a continuous count and update operation.
The value written to the fixed count bit field is copied, immediately to the running count, restarting any
existing running count operation. When the new running count reaches 0, it freezes.
The value written to the fixed count bit field is copied, immediately to the running count, restarting any
existing running count operation. When the new running count reaches 0, it is reloaded from the value
in the fixed count bit field, therefore running continuously using the newly supplied fixed count.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RUNNING
for programming details.
Table 23-1. Timer State Machine Transitions
Chapter 23 Timers and Rotary Decoder (TIMROT)
Interrupt Collector
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