MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1574

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Functional Description
Exiting Stop Mode is done in one of the following ways:
In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time
FlexCAN entered Stop Mode, then upon detection of a recessive to dominant transition on
the CAN bus, FlexCAN sets the WAK_INT bit in the ESR Register and, if enabled by the
WAK_MSK bit in MCR, generates a Wake Up interrupt to the ARM. Upon receiving the
interrupt, the ARM should resume the clocks and remove the Stop Mode request. FlexCAN
will then wait for 11 consecutive recessive bits to synchronize to the CAN bus. As a
consequence, it will not receive the frame that woke it up.
SLF_WAK and WAK_MSK upon wake-up from Stop Mode. Note that wake-up from Stop
Mode only works when both bits are asserted.
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• Waits to be in either Idle or Bus Off state, or otherwise waits for the third bit of
• Waits for all internal activities like arbitration, matching, move-in and move-out to
• Ignores its Rx input pin and drives its Tx pin as recessive
• Sets the NOT_RDY and LPM_ACK bits in MCR
• Sends a Stop Acknowledge signal to the ARM, so that it can shut down the clocks
• ARM resuming the clocks and removing the Stop Mode request
• ARM resuming the clocks and Stop Mode request as a result of the Self Wake
Intermission and checks it to be recessive
finish
globally
mechanism
SLF_WAK
0
0
1
1
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 25-9. Wake-up from Stop Mode
WAK_MSK
0
1
0
1
Clocks Enabled
i.MX28
Yes
No
No
No
Table 25-9
Wake-up Interrupt Generated
Freescale Semiconductor, Inc.
details the effect of
Yes
No
No
No