MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1154
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
- MCIMX283DVM4B PDF datasheet #2
- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
Programmable Registers
14.8.51 DRAM Control Register 55 (HW_DRAM_CTL55)
This is a DRAM configuration register.
Address:
Re-
1154
set
CURRENT_BDW
Bit
W
AXI3_EN_SIZE_
R
AXI3_BDW_
AXI3_FIFO_
TYPE_REG
LT_WIDTH_
AXI3_BDW
PRIORITY
OVFLOW
31
AXI3_W_
0
RSVD4
RSVD3
RSVD2
RSVD1
RSVD2
INSTR
30 24
23 17
31 16
15 11
AXI3_
Field
14 8
Field
10 8
7 2
1 0
31
16
15
30
0
29
0
HW_DRAM_CTL55
28
AXI3_EN_SIZE_LT_WIDTH_INSTR
0
Always write zeroes to this field.
Current bandwidth usage percentage for port 3. READ-ONLY.
Always write zeroes to this field.
Port 3 behavior when bandwidth maximized.
Always write zeroes to this field.
Maximum bandwidth percentage for port 3.
Always write zeroes to this field.
Clock domain relativity between AXI port 3 and core logic.
Allow narrow instructions from AXI port 3 requestors with bit enabled.
Always write zeroes to this field.
Priority of write cmds from AXI port 3.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL54 field descriptions
HW_DRAM_CTL55 field descriptions
800E_0000h base + DCh offset = 800E_00DCh
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
RSVD2
13
0
12
0
11
0
10
PRIORITY
0
AXI3_W_
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
RSVD1
0
5
0
4
3
0
PRIORITY
0
2
AXI3_R_
0
1
0
0
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