MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2221

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 36
Sony-Philips Digital Interface Format Transmitter
(SPDIF)
36.1 Overview
The Sony-Philips Digital Interface Format (SPDIF) transmitter module transmits data
according to the SPDIF digital audio interface standard (IEC-60958).
block diagram of the SPDIF transmitter module.
Data samples are transmitted as blocks of 192 frames, each frame consisting of two 32-bit
sub-frames.
A 32-bit sub-frame is composed of a 4-bit preamble, a 24-bit data payload (that is, a left-
or right-channel PCM sample), and a 4-bit status field. The status fields are encoded
according to the IEC-60958 consumer specification, reflecting the contents of the
HW_SPDIF_FRAMECTRL and HW_SPDIF_CTRL registers. See the IEC-60958
specification for proper programming of these fields.
The sub-frame is transmitted serially, LSB-first, using a biphase-mark channel-coding
scheme. This encoding allows an SPDIF receiver to recover the embedded clock signal.
36.2 Operation
The SPDIF transmitter operates at one of three register-selectable base sample rates: 32
KHz, 44.1 KHz, or 48 KHz. Double-rate output (64 KHz, 88.2 KHz, and 96 KHz) can also
be selected using HW_SPDIF_SRR_BASEMULT. The data-clock required to transmit a
SPDIF frame at these sample-rates is generated using a fractional clock-divider. This divider
uses both edges of a 120 MHz clock, which is derived from a divide-by-4 of the PLL 480
Freescale Semiconductor, Inc.
Sub-frame information can be changed on-the-fly but is not
reflected in the serial stream until the current frame is transmitted.
This ensures consistency of the frame and the generated parity
appended to that frame.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Note
Figure 36-1
shows a
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