MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2039

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

32.2.6 Recommended Register Configuration for USB Certification
The register settings in this section are recommended for passing USB certification.
The following settings lower the J/K levels to certifiable limits:
Note that HW_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD is controlled by the
SFTRST and CLKGATE bits in the AUDIOIN block.
32.3 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
CLKGATE bit fields.
32.4 Programmable Registers
USBPHY Hardware Register Format Summary
USBPHY0 base address is 0x8007C000; USBPHY1 base address is 0x8007E000
Freescale Semiconductor, Inc.
8007_C000
8007_C010
8007_C020
8007_C030
8007_C040
8007_C050
8007_C060
8007_C070
8007_C080
Absolute
address
(hex)
HW_USBPHY_TX_TXCAL45DP = 0x0
HW_USBPHY_TX_TXCAL45DN = 0x0
HW_USBPHY_TX_D_CAL = 0x7
USB PHY Power-Down Register (HW_USBPHY_PWD)
USB PHY Transmitter Control Register (HW_USBPHY_TX)
USB PHY Receiver Control Register (HW_USBPHY_RX)
USB PHY General Control Register (HW_USBPHY_CTRL)
USB PHY Status Register (HW_USBPHY_STATUS)
USB PHY Debug Register (HW_USBPHY_DEBUG)
UTMI Debug Status Register 0
(HW_USBPHY_DEBUG0_STATUS)
UTMI Debug Status Register 1 (HW_USBPHY_DEBUG1)
UTMI RTL Version (HW_USBPHY_VERSION)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_USBPHY memory map
for additional information on using the SFTRST and
(in bits)
Width
32
32
32
32
32
32
32
32
32
Access
Chapter 32 Integrated USB 2.0 PHY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
001E_1C00h
C020_0000h
Reset value
1006_0607h
0000_0000h
0000_0000h
7F18_0000h
0000_0000h
0000_1000h
0402_0000h
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32.4.6/2048
32.4.7/2050
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