MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2018
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
- MCIMX283DVM4B PDF datasheet #2
- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
- Current page: 2018 of 2327
- Download datasheet (17Mb)
Programmable Registers
Address:
2018
Reset
Reset
Bit
Bit
W
W
R
R
RSVD6
RSVD5
RSVD4
RSVD3
31 24
22 20
19 18
Field
15 8
TXE
TXT
TXS
23
17
16
31
15
0
0
HW_USBCTRL_ENDPTCTRL0 8008_0000h base + 1C0h offset = 8008_
01C0h
30
14
0
0
Reserved.
TX Endpoint Enable.
1 = Enabled.
Endpoint0 is always enabled.
Reserved.
Bit reserved and should be read as zeroes.
TX Endpoint Transmit Type.
Endpoint0 is fixed as a Control endpoint.
0
Reserved.
Endpoint Stall.
0 = Endpoint OK (default).
1 = Endpoint Stalled.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. It will
continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt
of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.
Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware
continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However,
should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually
write this stall bit until it is set OR until a new SETUP has been received by checking the associated
ENDPTSETUPSTAT bit.
Reserved.
CONTROL — Control.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBCTRL_ENDPTCTRL0 field descriptions
28
12
0
0
RSVD6
RSVD3
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
RXE
TXE
23
1
1
7
22
0
0
6
RSVD5
RSVD2
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
RXT
TXT
18
0
0
2
RSVD4
RSVD1
17
0
0
1
RXS
TXS
16
0
0
0
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