MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 998

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 16-113
16.5.3.10.5 Timer Event Mask Register (TMR_PEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_PEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset.
the definition for the TMR_PEMASK register.
16-114
Offset eTSEC1:0x2_4E10
Reset
Reset
24–30
0–21
Bits
Offset eTSEC1:0x2_4E0C
Reset
Reset
22
23
31
W
W
R
R
W
W
R
R
16
0
16
0
Name
TXP2
TXP1
RXP
describes the fields of the TMR_PEVENT register fields for the timer.
—
—
Reserved
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
Reserved
Indicates that a PTP frame has been received
0 PTP packet not received
1 PTP packet has been received
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
—
Table 16-113. TMR_PEVENT Register Field Descriptions
—
Figure 16-108. TMR_PEMASK Register Definition
Figure 16-107. TMR_PEVENT Register Definition
21
21
TXP2EN TXP1EN
22
TXP2 TXP1
22
All zeros
All zeros
All zeros
All zeros
—
—
23
23
Description
24
24
—
—
Figure 16-108
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
30
30
describes
RXP
RXPEN
15
31
15
31