MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1138

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
4
Complete List of Configuration, Control, and Status Registers
A.2
A-2
1
2
Depends on reset configuration word high values. See
Depends on reset configuration word high values. See
for details.
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
Value,”
Bit #25 depends on the RCW.
Bit #30 depend on RCW.
Local Memory
0x0B0–0x0FC
Local Memory
0x160–0x1FC
Offset (Hex)
0x11C–0x124
Offset (Hex)
0x0AC
0x0A8
for details.
0x10C
0x12C
0x100
0x104
0x108
0x110
0x114
0x118
0x128
0x140
0x144
0x148
System Configuration Registers
DDR2 local access window 1 base address register
(DDRLAWBAR1)
DDR2 local access window 1 attribute register
(DDRLAWAR1)
Reserved
System general purpose register low (SGPRL)
System general purpose register high (SGPRH)
System part and revision ID register (SPRIDR)
Reserved
System priority configuration register (SPCR)
System I/O configuration register low (SICRL)
System I/O configuration register high (SICRH)
Reserved
DDR control driver register (DDRCDR)
DDR debug status register (DDRDSR)
PCI Express control register 1 (PECR1)
eSDHC Control Regiser (SDHCCR)
RTC Control Register (RTCCR)
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table A-1. Local Access Register Memory Map (continued)
System Configuration—Block Base Address 0x0_000
Table A-2. System Configuration Registers
Local Access—Block Base Address 0x0_000
Register
Register
Section 5.1.4.4.1, “LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,”
Section 5.1.4.3.1, “LBLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.1.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.1.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
R
R
Access
R/W
R/W
—
0x0000_0000
0x0014_5000
0x0000_0000
0x0000_0000
0x8101_0010
0x0000_0000
0x7304_0001
0x3300_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
Reset
Freescale Semiconductor
—
1
2
Section/Page
5.2.2.10/5-27
5.2.2.11/5-28
5.2.2.12/5-29
5.2.2.13/5-31
5.2.2.1/5-16
5.2.2.2/5-16
5.2.2.3/5-17
5.2.2.4/5-17
5.2.2.5/5-19
5.2.2.6/5-22
5.2.2.9/5-26
Section/Page
5.1.4.7/5-11
5.1.4.8/5-12
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—
—
for details.
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for