MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 225

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3
The following sections describe arbitration policy and bus error detection.
6.3.1
The arbitration process involves the masters and the arbiter. Masters arbitrate on the privilege to own an
address tenure. For data tenures, the arbiter uses the same order of transactions as address tenures.
Figure 6-9
arbitration.
Freescale Semiconductor
Bits
28
29
30
31
Functional Description
Name
ECW
DTO
ATO
shows the interface signals between the arbiter and masters that are involved in address bus
AO
Arbitration Policy
External control word transfer type. Transaction with external control word transfer type interrupt
definition.
0 Transaction with external control word transfer type causes interrupt.
1 Transaction with external control word transfer type causes reset request.
Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes interrupt.
1 Transaction with address only transfer type causes reset request.
Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes interrupt.
1 Data tenure time out causes reset request.
0 Address tenure time out causes interrupt.
1 Address tenure time out causes reset request.
Address time out. Address tenure time out interrupt definition.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Master N
Master 1
Master 2
•
•
•
Figure 6-9. Address Bus Arbitration
Table 6-9. AERR Field Descriptions
PRIORITY[0:1]
PRIORITY[0:1]
PRIORITY[0:1]
REPEAT
REPEAT
REPEAT
BR
BG
BR
BG
BR
BG
Description
Arbiter
Arbiter and Bus Monitor
6-11