MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1145

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.14 I
A.15 DUART
Freescale Semiconductor
1
Implementation-dependent reset values are listed in specified section/page.
0x01C–0x1FF
Offset
0x500
0xE4C
Offset
0xE20
0xE24
0xE28
0xE40
0xE44
0xE48
0xE50
0xE54
0xE58
Offset
0x00C
0x000
0x004
0x008
0x010
0x014
2
C Controller
URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte register
CAPTURE_DATA_HI—Memory data path read capture high
CAPTURE_DATA_LO—Memory data path read capture low
CAPTURE_ECC—Memory data path read capture ECC
ERR_DETECT—Memory error detect
ERR_DISABLE—Memory error disable
ERR_INT_EN—Memory error interrupt enable
CAPTURE_ATTRIBUTES—Memory error attributes capture
CAPTURE_ADDRESS—Memory error address capture
ERR_SBE—Single-Bit ECC memory error management
Reserved
I2CFDR—I
I2CCR—I
I2CDR—I
I2CDFSRR—I
I2CADR—I
I2CSR—I
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table A-13. DDR Memory Controller Registers (continued)
DDR Memory Controller—Block Base Address 0x0_2000
2
2
2
C status register
C control register
C data register
2
2
C frequency divider register
C address register
I
I
2
2
2
C Controller 1 —Block Base Address 0x0_3000
C Controller 2 —Block Base Address 0x0_3100
C digital filter sampling rate register
UART 1—Block Base Address 0x0_4000
UART 2—Block Base Address 0x0_4100
Table A-14. I
Table A-15. DUART Registers
Register
Register
Register
2
C Controller Registers
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
—
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
Access
R/W
W
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000
0x0000
0x0000
0x0081
0x0000
0x0010
Reset
—
Reset
0x0000
0x0000
0x0000
—
Reset
17.3.1.6/17-10
Section/Page
17.3.1.1/17-5
17.3.1.2/17-5
17.3.1.3/17-6
17.3.1.4/17-8
17.3.1.5/17-9
Section/Page
Section/Page
18.3.1.1/18-5
18.3.1.2/18-5
18.3.1.3/18-6
9.4.1.21/9-32
9.4.1.22/9-32
9.4.1.23/9-33
9.4.1.24/9-33
9.4.1.25/9-34
9.4.1.26/9-35
9.4.1.27/9-36
9.4.1.28/9-37
9.4.1.29/9-37
—
—
A-9