MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 565

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 12-21
Figure 12-21
Freescale Semiconductor
Offset DMA_Offset = 0x1000 + (32 x n ) + 0x18
Reset
Reset
W
W
R
R
30–25
24–16
15–0
Bits
31
31
15
describes the TCD word 5 fields.
shows the TCD word 6 field.
citer.linkch[5–0]
citer[14–9] or
citer.e_link
doff[15–0]
citer[8–0]
Name
Table 12-21. TCD Word 5 (TCD.{citer, doff} Field Descriptions
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 12-21. TCD Word 6 (TCDn.dlast_sga) Field
Enable channel-to-channel linking on minor loop complete. As the channel completes the
inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[5:0].
The link target channel initiates a channel service request via an internal mechanism that
sets the TCD.start bit of the specified channel. If channel linking is disabled, the citer value
is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this
link mechanism is suppressed in favor of the major.e_link channel linking. This bit must be
equal to the biter.e_link bit otherwise a configuration error is reported.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Current major iteration count or link channel number.
If (TCD.citer.e_link = 0) then no channel-to-channel linking (or chaining) is performed
after the inner minor loop is exhausted. TCD word 5, bits [30:25] are used to form a 15 bit
citer field. Otherwise, after the minor loop is exhausted, the DMA engine initiates a channel
service request at the channel defined by citer.linkch[5:0] by setting that channel’s
TCD.start bit.
The value contained in citer.linkch[5:0] must not exceed the number of implemented
channels.
Current major iteration count. This 9 or 15-bit count represents the current major loop count
for the channel. It is decremented each time the minor loop is completed and updated in the
transfer control descriptor memory. Once the major iteration count is exhausted, the channel
performs a number of operations (e.g., final source and destination address calculations),
optionally generating an interrupt to signal channel completion before reloading the citer field
from the beginning iteration count (biter) field.
When the citer field is initially loaded by software, it must be set to the same value as that
contained in the biter field.
If the channel is configured to execute a single service request, the initial values of biter and
citer should be 0x0001.
Destination address signed offset. Sign-extended offset applied to the current destination
address to form the next-state value as each destination write is completed.
dlast_sga[31–16]
dlast_sga[15–0]
All zeros
All zeros
Description
DMA Controller (DMAC)
Access: Read/Write
12-21
16
0