MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1104

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DUART
Table 18-20
Table 18-22
18.4
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock signal.
18-16
DMS
DMS
DMS
DMS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FEN
FEN
FEN
FEN
Functional Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
and
and
Table 18-21
Table 18-23
DMA Mode
DMA Mode
DMA Mode
DMA Mode
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.
TXRDY is set when the transmitter FIFO is full.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY
remains clear while the transmitter FIFO is not yet full.
RXRDY is set when there are no characters in the receiver FIFO or URBR.
RXRDY is set when the trigger level has not been reached and there has been no time out.
RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.
RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains
cleared until the receiver FIFO is empty.
show the set and cleared conditions for UDSR[TXRDY].
show the set and cleared conditions for UDSR[TRRDY].
Table 18-21. UDSR[TXRDY] Cleared Conditions
Table 18-22. UDSR[RXRDY] Set Conditions
Table 18-20. UDSR[TXRDY] Set Conditions
Table 18-23. UDSR[RXRDY] Cleared
Meaning
Meaning
Meaning
Meaning
Freescale Semiconductor