MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 80

MPU POWERQUICC II PRO 473MAPBGA

MPC8308VMAGD

Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC8308VMAGD

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Overview
1.2.11
The device includes a Dual universal Asynchronous Reciever/Transmitter (DUART) intended for use in
maintenance, bring up, and debug systems. The device provides a standard two-wire data (TXD and RXD)
for each port. The DUART is a slave interface. An interrupt is provided to the interrupt controller.
Interrupts are generated for transmit, receive, and line status.
The DUART supports full-duplex operation. It is compatible with the PC16450 and PC16550
programming models. The transmitter and receiver both support 16-byte FIFOs.
Software programmable baud rate generators divide the system clock to generate a 16x clock. Serial
interface data formats (data length, parity, 1/1.5/2 STOP bit, baud rate) are also software selectable.
The DUART includes the following features:
1.2.12
The enhanced secure digital host controller (eSDHC) provides an interface between the host system and
these types of memory cards:
1-16
Full-duplex operation
Programming model compatible with the original PC16450 UART and the PC16550D (an
improved version of the PC16450 that also operates in FIFO mode)
PC16450 register reset values
FIFO mode for both transmitter and receiver, providing 16-byte FIFOs
Serial data encapsulation and decapsulation with standard asynchronous communication bits
(START, STOP, and parity)
Maskable transmit, receive, and line status interrupts
Software-programmable baud rate generators that divide the system clock by 1 to (2
generate a 16x clock for the transmitter and receiver engines
Software-selectable serial-interface data format (data length, parity, 1/1.5/2 STOP bit, baud rate)
Line status registers
Line-break detection and generation
Internal diagnostic support, local loopback, and break functions
Prioritized interrupt reporting
Overrun, parity, and framing error detection
MultiMediaCard (MMC)
MMC is a universal low-cost data storage and communication medium designed to cover a wide
area of applications including mobile video and gaming, which are available from either pre-loaded
MMC cards or downloadable from cellular phones, WLAN, or other wireless networks.
Secure digital (SD) card
The secure digital (SD) card is an evolution of old MMC technology. It is specifically designed to
meet the security, capacity, performance, and environment requirements inherent in the emerging
Dual Universal Asynchronous Receiver/Transmitter (DUART)
Enhanced Secure Digital Host Controller (eSDHC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor
16
– 1) and

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