MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1097

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 18-7
Table 18-10
The bits contained in the UIIR registers are described in
18.3.1.6
UFCR is used to enable and clear the receiver and transmitter FIFOs, set a receiver FIFO trigger level to
control the received data available interrupt, and select the type of DMA signaling.
Freescale Semiconductor
Offset: 0x0_4502, 0x0_4602
Bits
IID3–
0–1
2–3
5–6
0001
0110
0100
1100
0010
Reset
IID0
4
7
W
R
IID2–IID1
Priority
Highest
Second
Second
Name
Level
Third
IID3
IID0
FE
—
—
shows the bits in the UIIR.
describes the fields of the UIIR.
0
0
FIFO Control Registers (UFCR1 and UFCR2)
Received data available Receiver data available or trigger level
FE
FIFOs enabled. Reflects the setting of UFCR[FEN].
Reserved
Interrupt ID bits identify the highest priority interrupt that is pending as indicated in
set along with IID2 only when a time out interrupt is pending for FIFO mode.
Interrupt ID bits identify the highest priority pending interrupt as indicated in
IID0 indicates when an interrupt is pending.
0 The UART has an active interrupt ready to be serviced.
1 No interrupt is pending.
Receiver line status
Character time-out
Interrupt Type
UTHR empty
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
0
1
Figure 18-7. Interrupt ID Registers (UIIR1 and UIIR2)
—
Table 18-10. UIIR Field Descriptions
Table 18-11. UIIR IID Bits Summary
0
2
Overrun error, parity error, framing error, or
break interrupt
reached in FIFO mode.
No characters were removed from or input to
the receiver FIFO during the last four
character times and at least one character is
in the receiver FIFO.
Transmitter holding register is empty.
—
Interrupt Description
0
3
Description
Table
—
IID3
0
4
18-11.
IID2
5
0
Reading the line status register
Reading the receiver buffer
register or if the number of
bytes in the receiver FIFO
drops below the trigger level.
Reading the receiver buffer
register
Reading UIIR or writing to
UTHR
Table
How To Reset Interrupt
IID1
Access: User read-only
0
18-11.
6
Table
—
18-11. IID3 is
IID0
1
7
DUART
18-9