MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 392

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
Enhanced Local Bus Controller
10.3.1.2.2
Figure 10-3
Table 10-7
10-12
Offset OR0: 0x0_5004
Reset
Reset
17–18
0–16
Refer to
Bits
19
20
W
W
R
R
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
AM
16
0
BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
Name
CSNT Chip select negation time. Determines when LCS n and LWE are negated during an external memory write
Table 10-5
AM
—
describes ORn fields for GPCM mode.
shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM machine.
17
Option Registers (OR n )—GPCM Mode
GPCM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked and therefore don’t care for address checking.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
Reserved
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
access handled by the GPCM, provided that ACS ≠ 00 (when ACS = 00, only LWE is affected by the setting
of CSNT). This helps meet address/data hold times for slow memories and peripherals.
0 LCS n and LWE are negated normally.
1 LCS n and LWE are negated earlier depending on the value of LCRR[CLKDIV].
—
for the OR0 reset value. All other option registers have all bits cleared.
18
[CLKDIV]
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
LCRR
4 or 8
BCTLD CSNT
x
2
19
Figure 10-3. Option Registers (OR n ) in GPCM Mode
Table 10-7. OR n
20
CSNT
0
1
1
21
ACS
LCS n and LWE are negated normally.
LCS n and LWE are negated normally.
LCS n and LWE are negated one quarter bus clock cycle earlier.
22
—
XACS
GPCM Field Descriptions
23
All zeros
All zeros
AM
Description
24
SCY
Meaning
27
SETA
28
Freescale Semiconductor
TRLX
29
Access: Read/Write
EHTR
30
—
15
31