MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 297

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.5.14
SECNR, shown in
determines whether the corresponding IRQn signal asserts an interrupt request upon either a high-to-low
change or assertion on the pin. It also defines the IPIC output interrupt type (int, cint, or smi) in the
MIXA0–MIXA1 and MIXB0–MIXB1 priority positions.
Note that in core disabled mode of operation the user should use the int output interrupt type (should not
use cint or smi output interrupt types) in order to read an updated SIVCR.
Table 8-22
Freescale Semiconductor
Offset 0x3C
Reset
Reset
17–31
Bits
Bits
16
0–1
2–3
4–7
W
W
R
R
EDI0
SIRQ0 Steer IRQ0.
Name
16
0
MIXB0T
MIXB0T MIXB0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal ( int ,
MIXB1T Same as MIXB0T, but for MIXB1T.
—
Name
defines the bit fields of SECNR.
—
System External Interrupt Control Register (SECNR)
EDI1
17
0 IRQ0 is used as external interrupt request
1 IRQ0 is used as external MCP request
Write ignored, read = 0
1
cint , or smi ) asserts its request to the core in the MIXB0 priority position. These bits can be changed
dynamically. The definition of MIXB0T is as follows:
00 int request is asserted to the core for MIXB0.
01 smi request is asserted to the core for MIXB0.
10 cint request is asserted to the core for MIXB0.
11 Reserved
Write ignored, read = 0
Figure
EDI2
18
Figure 8-17. System External Interrupt Control Register (SECNR)
2
MIXB1T
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
EDI3
8-17, defines the edge detect mode for external IRQn interrupt signals and
19
3
Table 8-21. SEMSR Field Descriptions (continued)
20
4
Table 8-22. SECNR Field Descriptions
—
All zeros
All zeros
7
Description
Description
8
MIXA0T
9
Integrated Programmable Interrupt Controller (IPIC)
—
10
MIXA1T
11
12
Access: Read/write
—
15
31
8-23