MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 586

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.3.1.4
HCCPARAMS identifies multiple mode control (time-base bit functionality) addressing capability.
Figure 13-5
Table 13-7
13-8
Offset 0x108
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23–20
19–17
15–12
31–16
11–8
15–8
Bits
Bits
7–5
3–0
7–4
16
4
3
W
R
31
N_PORTS
Name
EECP
N_PCC
N_PTT
IST
N_CC
Name
—
—
provides bit descriptions for the HCCPARAMS register.
PPC
shows the HCCPARAMS register.
—
—
PI
Host Controller Capability Parameters (HCCPARAMS)
Reserved, should be cleared.
EHCI extended capabilities pointer. Indicates the existence of a capabilities list. A value of 0x00 indicates
no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
Isochronous scheduling threshold. Indicates, relative to the current position of the executing host controller,
where software can reliably update the isochronous schedule. When bit 7 is zero, the value of the least
significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data
structures (one or more) before flushing the state. When bit 7 is a one, then host software assumes the host
controller may cache an isochronous data structure for an entire frame.
This field is always 0.
Reserved, should be cleared.
Ports per transaction translator. This is a non-EHCI field. The number of ports assigned to each
transaction translator. This is equal to N_PORTS.
Reserved, should be cleared.
Port indicators. Indicates whether the ports support port indicator control. Always 1.
1 The port status and control registers include a R/W field for controlling the state of the port indicator.
Number of companion controllers associated with the DR controller. Always 0.
Number ports per CC. This field indicates the number of ports supported per internal companion
controller. Always 0.
Reserved, should be cleared.
Power port control. Indicates whether the host controller supports port power control. Always 1.
1 Ports have power port switches.
Number of ports. Number of physical downstream ports implemented for host applications. The value
of this field determines how many port registers are addressable in the operational register. Always 1.
Table 13-6. HCSPARAMS Register Field Descriptions (continued)
Figure 13-5. Host Control Capability Parameters (HCCPARAMS)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 13-7. HCCPARAMS Register Field Descriptions
—
0
16 15
0 0 0 0 0 0 0 0 0 0 0 0
Description
Description
EECP
8
7
IST
Freescale Semiconductor
0
4
—
Access: Read-only
0
3
ASP PFL ADC
1
2
1
1
0
0