MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 121

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3.2.2.1
BMS defines the initial value of the e300 core MSR[IP] bit, which specifies the location of the interrupt
vectors (including the hard reset exception vector). The device defines the default boot ROM memory
space to be 8 Mbytes at addresses 0x0000_0000 to 0x007F_FFFF or 0xFF80_0000 to 0xFFFF_FFFF.
When the core comes out of reset, if it is enabled to boot, it fetches boot code from one of two addresses,
0x0000_0100 or 0xFFF0_0100, and exceptions are vectored to the physical addresses, 0x000n_nnnn or
0xFFFn_nnnn appropriately. This bit specifies whether an interrupt vector offset is prepended with 0xFFF
or 0x000. In the description below, n_nnnn is the offset of the exception vector.
The boot memory space reset configuration word field, shown in
ROM address window and the initial e300 core boot address.
Freescale Semiconductor
RCWHR Bit Field Name
12–13
14–15
16–18
19–21
22–27
29–31
Bits
28
5
TSEC1M
TSEC2M
RLEXT
Name
TLE
—
—
—
Boot Memory Space (BMS)
BMS
Table 4-10. Reset Configuration Word High Bit Settings (continued)
Boot ROM location extension.
This bit combined with bit ROMLOC determines where the device boots from. See
“Boot ROM Location,”
00 Legacy mode—allows for booting from on-chip peripherals. For more information, see
01 NAND Flash mode—allows for booting from NAND flash devices. For more information, see
10 Reserved
11 Reserved
Reserved, should be cleared.
TSEC1 mode
See
TSEC2 mode.
See
Reserved, should be cleared.
True little-endian. See
Reserved, should be cleared.
Table
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Section 4.3.2.2.4, “eTSEC1 Mode,”
Section 4.3.2.2.5, “eTSEC2 Mode,”
(Binary)
Value
4-13.
0
1
Boot memory space is 8 Mbytes at 0x0000_0000 to 0x007F_FFFF.
e300 core register MSR[IP] initial value is 0b0.
The core, if enabled to boot, begins fetching boot code from address 0x0000_0100
and exceptions are vectored to the physical address of 0x000 n_nnnn .
Boot memory space is 8 Mbytes at 0xFF80_0000 to 0xFFFF_FFFF.
e300 core register MSR[IP] initial value is 0b1.
The core, if enabled to boot, begins fetching boot code from address 0xFFF0_0100
and exceptions are vectored to the physical address of 0xFFF n_nnnn .
Table 4-11. Boot Memory Space
for more information.
Section 4.3.2.2.6, “e300 Core True Little-Endian,”
for more information.
for more information.
Description
Table
Meaning
4-11, specifies both the device boot
Reset, Clocking, and Initialization
for more information.
Section 4.3.2.2.3,
Table
4-13.
4-13