MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 460

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
10.4.4.4.7
When a read access is handled by the UPM, and the UTA bit is 1 (data is to be sampled by the eLBC), the
value of the DLT3 bit in the same RAM word, in conjunction with MxMR[GPL4], determines when the
data input is sampled by the eLBC as follows:
Figure 10-67
10.4.4.4.8
When the LAST bit is read in a RAM word, the current UPM pattern is terminated at the end of the current
cycle. On the next cycle (following LAST) all the UPM signals are negated unconditionally (driven to
logic 1), unless there is a back-to-back UPM request pending. In this case, the signal values for the cycle
following the one in which the LAST bit was set are taken from the first RAM word of the pending UPM
routine.
10-80
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To internal
data bus
When UTA and REDO are set together, TA is asserted the number of times specified by the REDO
function.
When NA and REDO are set together, the address is incremented the number of times specified by
the REDO function.
When LOOP and REDO are set together, the loop mechanism works as usual and the line is
repeated according to the REDO function.
LAST and REDO must not be set together.
REDO should not be used within the exception routine.
If MxMR[GPL4] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data is
latched on the falling edge of the bus clock instead of the rising edge. The eLBC samples the data
on the next falling edge of the bus clock, which is during the middle of the current bus cycle. This
feature should be used only in systems without external synchronous bus devices that require
mid-cycle sampling.
If MxMR[GPL4] = 0 (G4T4/DLT3 functions as G4T4), or if MxMR[GPL4] = 1 but DLT3 = 0 in
the RAM word, data is latched on the rising edge of the bus clock, which occurs at the end of the
current bus clock cycle (normal operation).
shows how data sampling is controlled by the UPM.
Data Valid and Data Sample Control (UTA)
LGPL[0:5] Signal Negation (LAST)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
UPM read AND GPL4nDIS = 1 AND DLT3 = 1
Figure 10-67. UPM Read Access Data Sampling
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LCLK
Freescale Semiconductor
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