MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 206

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration
Table 5-62
5.6.5.7
The global timers prescale registers (GTPSR1, GTPSR2, GTPSR3, and GTPSR4) are shown in
Figure
Erratic behavior may occur if GTPSRn is not initialized before the corresponding GTMDRn.
Table 5-63
5-64
Offset
0–13
8–15
Bits
Bits
0–7
14
15
Reset
W
R
5-50.
Name
0x38(GTPSR1)
0x3A(GTPSR2)
Name
CAP
REF
PPS
—
—
0
0
defines the bit fields of GTEVRn.
defines the bit fields of GTPSRn.
Global Timers Prescale Registers (GTPSR1–GTPSR4)
The total timer prescale value is calculated as follows:
This gives a total prescale range from 1 (GTPSRn[PPS] = 0x00,
GTMDRn[SPS] = 0x00) to 65,536 (GTPSRn[PPS] = 0xFF,
GTMDR[SPS] = 0xFF).
GTMn
Output reference event
0 No event
1 The counter reached the GTRFR n [TRV] value. GTMDR n [ORI] is used to enable the interrupt request
Counter capture event
Corresponding timer’s 16-bit read/write up-counter value.
0 No event
1 The counter value has been latched into the GTCPR n [LCV]. GTMDR n [CE] is used to enable generation
Reserved, should be cleared.
Primary prescaler bits
The primary prescaler is programmed to divide the clock input to corresponding timer by values from 1 to 256.
The value 0x00 divides the clock by 1 and 0xFF divides the clock by 256.
Reserved, should be cleared.
0
caused by this event.
of this event.
Figure 5-50. Global Timers Prescale Registers (GTPSR1–GTPSR4)
prescale r
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
0x3C(GTPSR3)
0x3E(GTPSR4)
=
0
(
—
GTPSRn PPS
0
Table 5-62. GTEVR n Bit Settings
Table 5-63. GTPSR n Bit Settings
[
0
]
+
0
1
)
NOTE
⋅
(
GTMDRn SPS
0
7
Description
Description
0
8
[
0
]
+
1
)
0
0
PPS
0
Freescale Semiconductor
Access: Read/Write
0
1
15
1