MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 459

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The uppermost byte select (LBS0), when asserted, indicates that LD[0:7] contains valid data during a
cycle. Likewise, LBS1 indicates that LD[8:15] contain valid data. For a UPM refresh timer request, all
LBS[0:1] signals are asserted/negated by the UPM according to the refresh pattern only. Following any
internal bus monitor exception, the LBS[0:1] signals are negated regardless of the exception handling
provided by any UPM exception pattern to prevent spurious writes to external RAM.
10.4.4.4.4
The general-purpose signals (LGPL[0:5]) each have two bits in the RAM word that define the logical value
of the signal to be changed at the rising edge of the bus clock and/or at the falling edge of the bus clock.
LGPL0 offers enhancements beyond the other LGPLn lines.
LGPL0 can be controlled by an address line specified in MxMR[G0CL]. To use this feature, G0H and G0L
should be set in the RAM word. For example, for a SIMM with multiple banks, this address line can be
used to switch between internal memory device banks.
10.4.4.4.5
The LOOP bit in the RAM word specifies the beginning and end of a set of UPM RAM words that are to
be repeated. The first time LOOP = 1, the memory controller recognizes it as a loop start word and loads
the memory loop counter with the corresponding contents of the loop field shown in
RAM word for which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is
decremented by one.
Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word
executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word.
Loops can be executed sequentially but cannot be nested.
Also, special care must be taken that LAST and LOOP must not be set together.
10.4.4.4.6
The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise need too
many RAM words. Setting the REDO bits of the RAM word to a nonzero value causes the UPM to
re-execute the current RAM word up to three more times, as defined in the REDO field of the current RAM
word.
Special care must be taken in the following cases:
Freescale Semiconductor
General-Purpose Signals (G n T n , GO n )
Loop Control (LOOP)
Repeat Execution of Current RAM Word (REDO)
Read single-beat cycle
Read burst cycle
Write single-beat cycle
Write burst cycle
Refresh timer expired
RUN command
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
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Table 10-41. M x MR Loop Field Use
Loop Field
WLF
WLF
RLF
RLF
RLF
TLF
Enhanced Local Bus Controller
Table
10-41. The next
10-79