MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 627

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.5.3.1
The first DWord of an iTD is a pointer to the next schedule data structure, as shown in
Freescale Semiconductor
1
2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
31–5
Bits
4–3
2–1
Host controller read/write; all others read-only.
These fields may be modified by the host controller if the I/O field indicates an OUT.
0
Status
Status
Status
Status
Status
Status
Status
Status
1
1
1
1
1
1
1
1
Link Pointer Correspond to memory address signals [31:5], respectively. This field points to another isochronous
Name
Typ
—
T
Next Link Pointer
transaction descriptor (iTD/siTD) or queue head (QH).
Reserved, should be cleared. These bits are reserved and their value has no effect on operation.
Software should initialize this field to zero.
Indicates to the host controller whether the item referenced is an iTD, siTD or a QH. This allows the host
controller to perform the proper type of processing on the item after it is fetched. Value encodings are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate
1 Link Pointer field is not valid.
0 Link Pointer field is valid.
Transaction 0 Length
Transaction 1 Length
Transaction 2 Length
Transaction 3 Length
Transaction 4 Length
Transaction 5 Length
Transaction 6 Length
Transaction 7 Length
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Buffer Pointer (Page 5)
Buffer Pointer (Page 6)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 13-38. Isochronous Transaction Descriptor (iTD)
Table 13-40. Next Schedule Element Pointer
Next Link Pointer
1
1
1
1
1
1
1
1
ioc
ioc
ioc
ioc
ioc
ioc
ioc
ioc
15
14 13 12
PG
PG
PG
PG
PG
PG
PG
PG
Description
2
2
2
2
2
2
2
2
I/O
11
EndPt
10
9
Transaction 0 Offset
Transaction 1 Offset
Transaction 2 Offset
Transaction 3 Offset
Transaction 4 Offset
Transaction 5 Offset
Transaction 6 Offset
Transaction 7 Offset
8
Maximum Packet Size
Reserved
R
7
Reserved
Reserved
Reserved
Reserved
6
Universal Serial Bus Interface
Device Address
5
4
00
Table
3
2
2
2
2
2
2
2
2
2
Typ
13-40.
1
Mult
T 0x00
0
0x0C
0x1C
0x2C
0x3C
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
offset
13-49