MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 423

MPU POWERQUICC II PRO 473MAPBGA

MPC8308VMAGD

Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC8308VMAGD

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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memory cycle are taken from ORn. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR
and SETA fields.
10.4.2.1
The basic GPCM read timing parameters that may be set by the ORn attributes are shown in
The read access cycle commences upon latching of the memory address and concludes when LBCTL
returns high to turn the local bus around for a subsequent address phase. Read data is captured by eLBC
on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases before the end of the
read access to provide additional hold time for the external memory.
Freescale Semiconductor
Figure 10-33. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8)
LBCTL
LCLK
LCS n
LCLK
LCS n
LOE
LOE
Notes:
GPCM Read Signal Timing
LD
LA
TA
LD
LA
TA
t RC = Read cycle time.
t ARCS = Address valid to read chip-select time.
t AOE = Address valid to output enable time.
ACS=10
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 10-34. GPCM General Read Timing Parameters
ACS=11
t ARCS
t AOE
Read Data
Read Data
t CSRP
t RC
Valid Address
Valid Address
t CSRP = Read chip-select assertion period.
t OEN = Output enable negated time.
t OEN
Enhanced Local Bus Controller
Figure
10-34.
10-43

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