MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 109

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4
Reset, Clocking, and Initialization
The reset, clocking, and control signals offer many options for operating the device. Various modes and
features can be configured during hard reset or power-on reset. Most configurable features are loaded to
the device through a reset configuration word, and a few device signals are used as reset configuration
inputs during the reset sequence.
4.1
The following sections describe the reset and clock signals in detail.
4.1.1
Table 4-1
the signals that also function as reset configuration signals.
Freescale Semiconductor
PORESET
HRESET
Signal
External Signals
describes the reset signals of the device.
Reset Signals
I/O
I/O Hard reset. Causes the device to abort all current internal and external transactions and set most
I
Power-on reset. Initiates the power-on reset flow that resets the device and configures various
attributes of the device, including its clock modes.
registers to their default values. HRESET can be asserted completely asynchronously with respect to
all other signals. The device can detect an external assertion of HRESET while the device is not
asserting hard reset. HRESET is an open-drain signal.
State Meaning Asserted—An external agent has triggered a power-on reset sequence.
State Meaning Asserted—An external agent or internal hardware has triggered a hard reset. The
Requirements An open-drain signal. An external pull-up is required.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Reset State Always input.
Reset State Output, driven low during power-on and hard reset flows. High impedance after reset
Timing For timing information, see PowerQUICC II Pro MPC8308 Hardware Specification .
Timing Assertion—Occur at any time, asynchronously to any clock.
Table 4-1. System Control Signals
Negated—No power-on reset.
internal hardware drives HRESET until the sequence completes.
Negated—No hard reset.
Negation—Must be asserted for at least 32 SYS_CLK_IN cycles.
flow completes.
Section 4.3.2, “Reset Configuration Words,”
Description
describes
4-1