MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 299

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 8-24
8.5.16
Each implemented bit in SERMR, shown in
source (MCP). The user masks an MCP by clearing and enables an interrupt by setting the corresponding
SERMR bit. When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of
the corresponding SERMR bit although no MCP request is passed to the core in this case. The SERMR
can be read by the user at any time.
Table 8-25
Freescale Semiconductor
0–31 INT n Each implemented bit in the SERSR, listed in
Offset 0x44
Reset
Bits Name
0–31
Bits
W
R
0
Name
INT n Each implemented SERMR bit, listed in
defines the bit fields of SERSR.
defines the bit fields of SERMR.
System Error Mask Register (SERMR)
(mcp). When an error interrupt signal is received, the interrupt controller sets the corresponding SERSR bit.
SERSR bits are cleared by writing ones to them. Unmasked event register bits should be cleared before clearing
SERSR bits. Because the user can only clear bits in this register, writing zeros to this register has no effect.
SERSR bits are cleared by power-on reset. Subsequent soft and hard resets do not affect SERSR bit states.
For unimplemented bits (listed as reserved in
The user masks an MCP by clearing and enables an interrupt by setting the corresponding SERMR bit.
When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of the SERMR
bit although no MCP request is passed to the core. The SERMR can be read by the user at any time.
Writes to unimplemented (reserved) bits are ignored; read = 0
Implemented bits reset to ones; unimplemented (reserved) bits reset to zeros.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 8-19. System Error Mask Register (SERMR)
1
Table 8-25. SERMR Field Descriptions
Table 8-24. SERSR Field Descriptions
This bit is valid only if the IRQ0 signal is
configured as an external MCP interrupt
(SEMSR[SIRQ0] = 1)
INT
n (Implemented bits are listed in
Figure
Table
Table
Table
8-19, corresponds to an external and an internal mcp
Description
8-23, corresponds to an external and an internal MCP source.
8-23, corresponds to an external and an internal error source
8-23), writes are ignored, read = 0
Description
Integrated Programmable Interrupt Controller (IPIC)
Table
8-23.)
Access: Read/write
8-25
31