MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 856

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
n
Sixteen buses mean that the bus number can range from 0x00 to 0x0F. In general, if there are 2
bus
numbers to be configured, n number of address bits are needed to represent the variation of bus number
n
ranging from 0 to 2
– 1. For this example, four address bits from CSB[4–7] are required to represent the
bus number variation and therefore become the most significant four bits within the total 28 bit offset
(CSB[4–31], including reserved bits) of the outbound window to be configured. The CSB[0–3] in this case
will not participate in the bus number mapping process as shown in
Table
14-138, where all eight bits of
CSB[0–7] are mapped to PCI Express address bits [31–24] to represent the possible of 256 bus numbers
within a very large system. In other words, in the example, CSB[0–3] become the four most significant
bits of the base address of the outbound window to be configured and will be translated to a new “address”
in the PCI Express space as defined by the corresponding PEX_OWTARLn.
Based on the above information, the most significant four bits of the base address of the outbound window
came from CSB[0–3] must be unique within the total 4 Gbyte local CSB memory space. This essentially
defines a window with size of 256 Mbytes, since the lower 28 bits are offset. For this example, assume a
256 Mbyte outbound window is therefore defined between 0x5000_0000 and 0x5FFF_FFFF in local CSB
space. This yields the PEX_OWBARn’s BA[31–12] to be 0x5000_0, with the actual base address of the
outbound window as 0x5000_0000. The SIZE[31–12] field of the PEX_OWARn register is 0x1000_0 to
reflect the actual size of this outbound window as 0x1000_0000 or 256 Mbytes.
Note that the final configuration transaction to be generated is based on the information gathered from two
areas: the most significant four bits from the defined TAL (translation address low) bit field of
PEX_OWTARLn and the lower order bits from the CSB[4–31] offsets directly mapped to PCI Express
address bits [27–0]. As mention in the note section of
Table
14-138, software should ensure all the reserved
bits within CSB[4–31] are filled with zeros.
Since TAL[31–24] (total of eight bits) of PEX_OWTARLn could be used for mapping the bus number bit
field for a general configuration transaction, while in this example the bus number to be configured ranges
from 0x00 to 0x0F, the most significant four bits (TA[31–28]) are not needed for the bus number mapping
and therefore must be configured as 0x0. The TA[27–12] bit field of PEX_OWTARLn is left as all zeros.
This yields the PEX_OWTARLn’s TAL[31–12] to be 0x0000_0, with the actual translation address of the
outbound window as 0x0000_0000. Since the size of this window is 256 Mbytes, the upper limit of the
translation address is then locate at 0x0FFF_FFFF.
With the outbound window configured as above, if software intends to scan the PCI Express bus and
attempts to probe the first bus immediately underneath the PCI Express RC, the software will need to issue
a Configuration Transaction to read Register Number 0 (Vendor ID Register) at Bus Number/Device
Number/Function Number of 1/0/0, assuming the RC’s secondary bus number has been configured as 0x1
along with subordinate bus number being configured with a big number like 0xFF initially. As long as the
LAW is configured to ensure that the local address space between 0x5000_0000 and 0x5FFF_FFFF is
configured for PCI Express, a CSB-based memory read transaction to local address 0x5100_0000 initiated
by software will be translated to a transaction hitting PCI Express RC controller with PCI Express address
of 0x0100_0000. Upon receiving this CSB-based transaction, the RC controller checks the Type attribute
of this outbound window and realizes the transaction is of a configuration type, instead of directly using
the translated address as in usual memory transaction, the RC controller starts compose a configuration
transaction with header information from this translation address based on the mapping defined in
Table
14-138. The decode of the mapping process yields a type 0 configuration transaction to be generated
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
14-118
Freescale Semiconductor