MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 342

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 9-14
9.4.1.10
The DDR SDRAM mode 2 configuration register, shown in
DDR’s extended mode 2 and 3 registers (for DDR2).
Table 9-15
9-24
16–31 SDMODE SDRAM mode. Specifies the initial value loaded into the DDR SDRAM mode register. The range of legal
0–15 ESDMODE Extended SDRAM mode. Specifies the initial value loaded into the DDR SDRAM extended mode register.
16–31
Bits
0–15
Bits
Offset 0x11C
Reset
W
R
Name
ESDMODE2
ESDMODE3
0
describes the DDR_SDRAM_MODE fields.
describes the DDR_SDRAM_MODE_2 fields.
Name
Figure 9-11. DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)
DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)
The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence), MA[0]
presents the lsb of ESDMODE, which, in the big-endian convention shown in
ESDMODE[15]. The msb of the SDRAM extended mode register value must be stored at ESDMODE[0].
values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the lsb
of SDMODE, which, in the big-endian convention shown in
msb of the SDRAM mode register value must be stored at SDMODE[0]. Because the memory controller
forces SDMODE[7] to certain values depending on the state of the initialization sequence, (for resetting the
SDRAM’s DLL) the corresponding bits of this field are ignored by the memory controller. Note that
SDMODE[7] is mapped to MA[8].
Extended SDRAM mode 2. Specifies the initial value loaded into the DDR SDRAM extended 2 mode
register. The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during the DDR SDRAM initialization sequence),
MA[0] presents the lsb bit of ESDMODE2, which, in the big-endian convention shown in
corresponds to ESDMODE2[15]. The msb of the SDRAM extended mode 2 register value must be
stored at ESDMODE2[0].
Extended SDRAM mode 3. Specifies the initial value loaded into the DDR SDRAM extended 3 mode
register. The range of legal values of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus (during DDR SDRAM initialization), MA[0] presents the
lsb of ESDMODE3, which, in the big-endian convention shown in
ESDMODE3[15]. The msb of the SDRAM extended mode 3 register value must be stored at
ESDMODE3[0].
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 9-15. DDR_SDRAM_MODE_2 Field Descriptions
Table 9-14. DDR_SDRAM_MODE Field Descriptions
ESDMODE2
All zeros
15 16
Description
Description
Figure
Figure
9-11, sets the values loaded into the
9-10, corresponds to SDMODE[15]. The
ESDMODE3
Figure
Figure
9-11, corresponds to
Freescale Semiconductor
Access: Read/Write
9-10, corresponds to
Figure
31
9-11,