MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 435

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FCM asserts LCSn to commence a command sequence to the Flash device. After a delay of t
command can be written to the device on assertion of LFWE0, followed by any parameters (typically
address bytes and data), and concluded with a secondary command. In many cases, the second command
initiates a long-running operation inside the Flash device, which pulls the wired-OR pin LFRB low to
indicate that the device is busy. Since in
LBCTL low to turnaround any bus transceivers that are present. Upon LFRB indicating ready status, FCM
asserts LFRE repeatedly to recover bytes of read data, and the bytes are stored in eLBC’s FCM buffer
RAM while an ECC is optionally computed on the bytes transferred. Finally, FCM negates LCSn and
delays eLBC by t
10.4.3.1
Read and write accesses to eLBC banks controlled by FCM do not access attached NAND Flash
EEPROMs directly. Rather, these accesses read and write the FCM buffer RAM—a single, shared 8-Kbyte
space internal to eLBC and mapped by the base address of every FCM bank. Even though each
FCM-controlled bank will have a different base address to differentiate it, all accesses to such banks will
access the same buffer space. External eLBC signal, such as LCSn, will not assert upon accesses to the
buffer RAM. The FCM buffer RAM is logically divided into two or more buffers, depending on the setting
of ORn[PGS], with different buffers being accessible concurrently by software and FCM.
To perform a page read operation from a NAND Flash device, software initializes the FCM command,
mode, and address registers, before issuing a special operation (FMR[OP] set non-zero) to a particular
FCM-controlled bank. FCM executes the sequence of op-codes held in FIR, reading data from the Flash
device into the shared buffer RAM. While this read is taking place, software is free to access any data
stored in other, currently inactive buffers of the FCM buffer RAM through reads or writes to any bank
controlled by FCM. If command completion interrupts are enabled, an interrupt will be generated once
FCM has completed the read. When FCM has completed its last command, software can switch to the
newly read buffer and issue further commands.
To perform a page write operation, software first prepares data to be written in a fresh buffer. Then, the
FCM command, mode, and address registers are initialized, and a special operation (FMR[OP] set
non-zero) is issued to a particular FCM-controlled bank. FCM executes the sequence of op-codes held in
FIR, writing data from shared buffer RAM to the Flash device. To ensure that the device is enabled for
programming, software must initialize FMR[OP] = 11, which prevents assertion of LFWP during the
write. While this write is taking place, software is free to access any data stored in other, currently inactive
buffers of the FCM buffer RAM through reads or writes to any bank controlled by FCM. When FCM has
completed its last command, software can re-use the previously written buffer and issue further
commands.
See
buffer RAM layout during boot.
10.4.3.1.1
The FCM buffer space is divided into eight 1-Kbyte buffers for small-page devices (ORn[PGS] = 0),
mapped as shown in
512 bytes appear as main region data, and 16 bytes appear as spare region data. The EEPROM’s page
Freescale Semiconductor
Section 10.4.3.4.2, “Boot Block Loading into the FCM Buffer RAM,”
FCM Buffer RAM
Buffer Layout and Page Mapping for Small-Page NAND Flash Devices
EHTR
Figure
before any subsequent memory access occurs.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
10-46. Each page in a small-page NAND Flash comprises 528 bytes, where
Figure 10-45
FCM is now expecting a read response, it takes
for a description of the shared
Enhanced Local Bus Controller
CSCT
, the first
10-55