MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 958

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
16.5.3.5.12 Interface Status Register (IFSTAT)
Figure 16-46
Table 16-50
16.5.3.5.13 MAC Station Address Part 1 Register (MACSTNADDR1)
The MACSTNADDR1 register is written by the user. The value of the station address written into
MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a
frame in memory. For example, for a station address of 0x1234_5678_ABCD, MACSTNADDR1 is set to
0xCDAB_7856 and MACSTNADDR2 is set to 0x3412_0000.
Figure 16-47
Table 16-51
16-74
Offset eTSEC1:0x2_453C; eTSEC2:0x2_553C
Reset
23–31
0–21
Bits
8–15
22
Offset eTSEC1:0x2_4540; eTSEC2:0x2_5540
Reset
0–7
W
Bit
R
W
0
R
Excess Defer Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared by
0
Station Address, 6th Octet
Name
describes the fields of the FSTAT register.
describes the fields of the MACSTNADDR1 register.
shows the IFSTAT register.
shows the MACSTNADDR1 register.
—
—
Station Address, 6th Octet
Station Address, 5th Octet
Reserved
default.
0 Normal operation.
1 The MAC excessively defers a transmission.
Reserved
Figure 16-47. MAC Station Address Part 1 Register Definition
Name
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 16-46. Interface Status Register Definition
Table 16-51. MACSTNADDR1 Field Descriptions
7
Table 16-50. IFSTAT Field Descriptions
8
Station Address, 5th Octet
—
address bits 40
address bits 32
This field holds the sixth octet of the station address. The sixth octet (station
This field holds the fifth octet of the station address. The fifth octet (station
All zeros
All zeros
15 16
–
–
47) defaults to a value of 0x0.
39) defaults to a value of 0x0.
Description
Station Address, 4th Octet
21
Excess Defer
Description
22
23 24
23
Station Address, 3rd Octet
Freescale Semiconductor
Access: Read/Write
Access: Read only
—
31
31