MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 616

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.3.2.23 Endpoint Control Register n (ENDPTCTRL n )—Non-EHCI
The endpoint control n registers, shown in
is an ENDPTCTRLn register of each endpoint in a device.
Table 13-32
13-38
31–24
19–18
Offset 0x1C4 (ENDPTCTRL1), 0x1C8 (ENDPTCTRL2),
Reset
Bits
Bits
23
22
21
20
17
1
0
W
R
31
Name
Name
TXR
TXD
TXE
TXT
TXI
RXS
—
—
—
describes the endpoint control n register fields.
0 Disabled
1 Enabled
this bit in order to synchronize the data PID’s between the Host and device.
this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID sequencing enabled
1 PID sequencing disabled
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
engine as the source.
Reserved, should be cleared
TX endpoint enable
TX data toggle reset. Whenever a configuration event is received for this endpoint, software must write a one to
TX data toggle inhibit. Used only for test and should always be written as zero. Writing a one to this bit will cause
Reserved, should be cleared
TX endpoint type
TX endpoint data source. This bit should always be written as 0, which selects the dual port memory/DMA
—
Reserved, should be cleared.
RX endpoint stall
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will
continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of
a new SETUP request.
1 Endpoint stalled
0 Endpoint OK
Table 13-31. ENDPTCTRL0 Register Field Descriptions (continued)
24
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
TXE TXR TXI — TXT TXD TXS
Table 13-32. ENDPTCTRL n Register Field Descriptions
23
Figure 13-29. Endpoint Control 1 to 5 (ENDPTCTRL n )
22
21
20 19 18
Figure
17
13-29, are not defined in the EHCI specification. There
All zeros
16
Description
Description
15
—
8
RXE RXR RXI — RXT RXD RXS
7
6
Freescale Semiconductor
5
Access: Read/Write
4
3
2
1
0