MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 160

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration
whenever an internal unit requests mastership of the coherent system bus (CSB). The SPCR also includes
some other control functions.
Table 5-24
5-18
10–11
12–17
18-19
‘
Bits
0–1
3–7
2
8
9
Offset 0x00110
Reset
Reset
W
W
R
R
SEONAK_FIX
COREPR
TSECDP
defines the bit fields of SPCR.
Name
TBEN
OPT
EN_
16
0
—
—
—
—
—
17
1
Reserved. Should be cleared.
enable_se0nak_fix for USBDR
If set, disables the SOF reporting when in SE0_NAK test mode.
Reserved. Should be cleared.
Optimize. Setting this bit may enhance the performance of transactions issued to the internal coherent
system bus (CSB) by a master such as USB controller. Performance is enhanced by reading more
bytes on the bus than actually needed by the master in the case that this is more efficient. The user
may set this bit only if it is known that USB transactions sent to the internal CSB are not accessing
devices in which speculative reads may change the state of the device (for example, FIFOs in which
reading a byte may advance some internal counter).
0 No performance enhancement.
1 Performance enhancement by speculative reading is enabled.
e300 core time base unit enable
0 Time base unit is disabled.
1 Time base unit is enabled.
e300 core CSB request priority.
The priority level for the core in accessing the CSB can be chosen from four possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Reserved. Should be cleared
eTSEC Data Priority.
Selects the CSB request priority driven by eTSEC1 and eTSEC2 when it requires to transfer data on
this bus.
The level of priority can be chosen from four possible levels.
00 Level 0 (lowest priority)
01 Level 1
10 Level 2
11 Level 3 (highest priority)
Figure 5-13. System Priority Configuration Register (SPCR)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
EN_SEONAK_
TSECDP
FIX
18
2
Table 5-24. SPCR Bit Settings
19
3
TSECBDP TSECEP
20
21
All zeros
22
All zeros
23
7
Description
OPT
24
8
TBEN
9
COREPR
10
11
—
Freescale Semiconductor
12
Access: Read/Write
—
31
15