MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 678

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
one of the following events occur: The transaction translator responds to a complete-split transaction with
one of the following:
Each time the host controller visits a queue head in this state (once within the Execute Transaction state),
bit-wise ANDs QH[S-mask] with cMicroFrameBit to determine whether to execute a start-split. If the
result is non-zero, then the host controller issues a start-split transaction. If the PID Code field indicates
an IN transaction, the host controller must zero-out the QH[S-bytes] field. After the split-transaction has
been executed, the host controller sets up state in the queue head to track the progress of the complete-split
phase of the split transaction. Specifically, it records the expected frame number into QH[FrameTag] field,
sets C-prog-mask to zero (0x00), and exits this state. Note that the host controller must not adjust the value
of Cerr as a result of completion of a start-split transaction.
13.6.12.2.7 Periodic Interrupt—Do-Complete-Split
This state is entered unconditionally from the Do Start Split state after a start-split transaction is executed
on the bus. Each time the host controller visits a queue head in this state (once within the Execute
Transaction state), it checks to determine whether a complete-split transaction should be executed now.
There are four tests to determine whether a complete-split transaction should be executed.
13-100
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NAK. A NAK response is a propagation of the full- or low-speed endpoint's NAK response.
ACK. An ACK response is a propagation of the full- or low-speed endpoint's ACK response. Only
occurs on an OUT endpoint.
DATA 0/1. Only occurs for INs. Indicates that this is the last of the data from the endpoint for this
split transaction.
ERR. The transaction on the low-/full-speed link below the transaction translator had a failure (for
example, timeout, bad CRC, etc.).
NYET (and Last). The host controller issued the last complete-split and the transaction translator
responded with a NYET handshake. This means that the start-split was not correctly received by
the transaction translator, so it never executed a transaction to the full- or low-speed endpoint, see
Section 13.6.12.2.7, “Periodic Interrupt—Do-Complete-Split,”
Test A. cMicroFrameBit is bit-wise ANDed with QH[C-mask] field. A non-zero result indicates
that software scheduled a complete-split for this endpoint, during this microframe.
Test B. QH[FrameTag] is compared with the current contents of FRINDEX[7–3]. An equal
indicates a match.
Test C. The complete-split progress bit vector is checked to determine whether the previous bit is
set, indicating that the previous complete-split was appropriately executed. An example algorithm
for this test is provided below:
Algorithm Boolean CheckPreviousBit(QH.C-prog-mask, QH.C-mask, cMicroFrameBit)
Begin
-- Return values:
-- TRUE - no error
-- FALSE - error
--
Boolean rvalue = TRUE;
previousBit = cMicroframeBit logical-rotate-right(1)
-- Bit-wise anding previousBit with C-mask indicates
-- whether there was an intent
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
for the definition of 'Last'.
Freescale Semiconductor