MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 955

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.5.3.5.7
The MIIMCOM register is written by the user.
Table 16-45
Freescale Semiconductor
29–31
0–29
Bits
Bits
27
28
30
31
Offset eTSEC1:0x2_4524
Reset
W
R
Read Cycle Read cycle. This bit is cleared by default but is not self-clearing once set.
Scan Cycle Scan cycle. This bit is cleared by default.
MgmtClk
No Pre
Name
Name
0
—
—
describes the fields of the MIIMCOM register.
MII Management Command Register (MIIMCOM)
0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble.
1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32
Reserved
is 111.
000 1/4 of the eTSEC system clock divided by 8
001 1/4 of the eTSEC system clock divided by 8
010 1/6 of the eTSEC system clock divided by 8
011 1/8 of the eTSEC system clock divided by 8
100 1/10 of the eTSEC system clock divided by 8
101 1/14 of the eTSEC system clock divided by 8
110 1/20 of the eTSEC system clock divided by 8
111 1/28 of the eTSEC system clock divided by 8
Reserved
0 Normal operation.
1 The MII management continuously performs read cycles. This is useful for monitoring link fail, for
0 Normal operation.
1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the
Preamble suppress. This bit is cleared by default.
This field determines the clock frequency of the MII management clock (TSEC_MDC). Its default value
clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.
example.
PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register
Address]). The 0-to-1 transition of this bit also causes the MIIMIND[Busy] bit to be set. The read is
complete when the MIIMIND[Busy] bit clears. Data is returned in register MIIMSTAT[PHY Status].
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-44. MIIMCFG Field Descriptions (continued)
Figure 16-41. MIIMCOM Register Definition
Table 16-45. MIIMCOM Descriptions
—
Figure 16-41
All zeros
Description
Description
describes the definition for MIIMCOM.
Enhanced Three-Speed Ethernet Controllers
29
Scan Cycle
30
Access: Read/Write
Read Cycle
31
16-71