MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 315

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 8-30
Table 8-36
8.7.2.2
The MSIMR contains the mask bits for the message shared interrupt register interrupts. The mask bit
corresponding to a message shared interrupt register must be clear to enable interrupt generation when the
message input region is written and a bit in the message shared interrupt register is set. This is a read-write
register.
Figure 8-31
Table 8-37
Freescale Semiconductor
Offset 0xC0
Reset
Reset
Offset 0xF0
Reset
W
W
W
0–23
R SH31 SH30 SH29 SH28 SH27 SH26 SH25 SH24 SH23 SH22 SH21 SH20 SH19 SH18 SH17 SH16
R SH15 SH14 SH13 SH12 SH11 SH10 SH9
31–0
R
Bits
Bits
24
25
0xC4
0xC8
0xCC
0
16
0
describes the bits of the MSIRs.
describes the bits of the MSIMR.
shows the message shared interrupt registers.
shows the message shared interrupt mask register.
Message Shared Interrupt Mask Register (MSIMR)
Name
Name
17
1
SH n
M7
M6
—
18
Figure 8-31. Message Shared Interrupt Mask Register (MSIMR)
2
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 8-30. Message Shared Interrupt Register (MSIRs)
Message sharer n ( n = 31–0) has a pending interrupt.
Reserved.
Mask 7. Set to 1 masks interrupt generation for message shared interrupt register 7
Mask 6. Set to 1 masks interrupt generation for message shared interrupt register 6
19
3
0xD0
0xD4
0xD8
0xDC
20
4
Table 8-37. MSIMR Field Descriptions
Table 8-36. MSIRs Field Descriptions
21
5
—
22
6
SH8
23
7
All zeros
All zeros
All zeros
SH7
Description
24
Description
8
SH6
25
9
Integrated Programmable Interrupt Controller (IPIC)
SH5
10
26
23 24
SH4
11
27
M7 M6 M5 M4 M3 M2 M1 M0
25
SH3
12
28
26
SH2
Access: Read/Write
27
13
29
Access: Special
28
SH1
14
30
29
30
SH0
15
31
8-41
31