MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 223

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.7
The arbiter event address register (AEADR) reports the address of transaction that causes the error that is
specified in the event register. See
AEADR is cleared only by power-on reset. The address of the first error event is stored. Note that this
means that AEADR does not change its value when AER is not clear. As AEADR is not affected by soft
or hard reset, the software can read this register and determine the cause of the bus failure, even if the bus
Freescale Semiconductor
11–15
16–19
21–23
24–26
27–31
Bits
20
MSTR_ID Master ID.
TTYPE
TSIZE
Name
TBST
—
—
Arbiter Event Address Register (AEADR)
00000 e300 core data transaction
00001 Reserved
00010 e300 core instruction fetch
00011 Reserved
00100 TSEC1
00101 TSEC2
00110 Reserved
00111 USB
01000 Reserved
Note: Master ID reflects the source of transaction and is used for debug purpose.
Write reserved, read = 0
Transfer burst.
0 Burst transaction. Transfer size is greater than 8 bytes
1 Single-beat transaction. Transfer size is up to 8 bytes
Transfer size. Transfer size encoding depends on the value of the field TBST.
TBST = 1:
001 1 byte
010 2 bytes
011 3 bytes
100 4 bytes
101 5 bytes
110 6 bytes
111 7 bytes
000 8 bytes
Write reserved, read = 0
Transfer type.
00000 Address-only
00001 Address-only
00010 Single-beat or burst write
00011 Reserved
00100 Address-only
00101 Reserved
00110 Burst write
00111 Reserved
0100x Address-only
0101x Single-beat or burst read
0110x Address-only
01110 Burst read
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 6-7. AEATR Field Descriptions (continued)
Section 6.2.3, “Arbiter Event Register (AER),”
Description
01001 I2C (boot sequencer)
01010 JTAG
01011 Reserved
01100 eSDHC
01101–11100 Reserved
11101 PCI Express
11110 Reserved
11111 DMA
TBST = 0:
000 16 bytes
001 24 bytes
010 32 bytes
011–111 Reserved
01111 Reserved
10000 Address-only
1XX01 Reserved
10010 Single-beat write
1XX11 Reserved
10100 ecowx—Illegal single-beat write
10110 Reserved
11000 Address-only
11010 Single-beat or burst read
11100 eciwx—Illegal single-beat read
11110 Burst read
for more information.
Arbiter and Bus Monitor
6-9