MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 928

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 16-22
16.5.3.2.8
TBPTR0–TBPTR7 each contains the low-order 32 bits of the next transmit buffer descriptor address for
their respective TxBD ring.
of their ring’s associated TBASE when the TBASE register is written by software. Software must not write
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0–TBPTR7 can be
modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP
TRANSMIT command is issued and the frame completes its transmission) in order to change the next
TxBD eTSEC transmits.
Table 16-23
16-44
16–23
24–31
29–31
8–15
0–28
Bits
Bits
0–7
Offset eTSEC1:0x2_4184+8× n ; eTSEC2:0x2_5184+8× n
Reset
W
R
TBPTR n Current TxBD pointer for TxBD ring n . Points to the current BD being processed or to the next BD the
Name
WT4
WT5
WT6
WT7
Name
0
—
describes the fields of the TR47WT register.
describes the fields of the TBPTRn register.
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7)
Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT4 × 64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field
prevents transmission.
Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT5 × 64 bytes of data are scheduled for transmission from TxBD ring 5. Clearing this field
prevents transmission.
Weighting value for TxBD ring 6 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT6 × 64 bytes of data are scheduled for transmission from TxBD ring 6. Clearing this field
prevents transmission.
Weighting value for TxBD ring 7 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT7 × 64 bytes of data are scheduled for transmission from TxBD ring 7. Clearing this field
prevents transmission.
transmitter uses when it is idling. When the end of the TxBD ring is reached, eTSEC initializes TBPTR n to
the value in the corresponding TBASE n . The TBPTR register is internally written by the eTSEC’s DMA
controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed
successfully by the eTSEC. Note that the three least significant bits of this register are read-only and zero.
After an error condition, the eTSEC returns TBPTR n to point to the first BD of the frame partially transmitted.
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 16-18
Figure 16-18. TBPTR0–TBPTR7 Register Definition
Table 16-22. TR47WT Field Descriptions
Table 16-23. TBPTR n Field Descriptions
describes the TBPTR registers. These registers takes on the value
TBPTR n
All zeros
Description
Description
Freescale Semiconductor
Access: Read/Write
28 29
—
31