MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 727

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
13.8.6.2
The low frequency events include the interrupts shown in
any order because they do not occur often in comparison to the high-frequency interrupts.
13.8.6.3
Error interrupts are the least frequently occurring events. They should be placed last in the interrupt service
routine.
13.9
The host mode operation of the USB DR module is nearly EHCI-compatible with few minor differences.
For the most part, the module conforms to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in the following areas:
Freescale Semiconductor
USB Error Interrupt
System Error
Execution
It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service
Routine.
Order
•
1b
2
Interrupt
Embedded transaction translator—Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
Port Change
Sleep Enable (Suspend)
Reset Received
Table 13-95
Deviations from the EHCI Specifications
USB Interrupt
ENDPTCOMPLETE
SOF Interrupt
Low-Frequency Interrupts
Error Interrupts
Interrupt
Interrupt
shows the error interrupt events.
This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD
will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt
(w/ ENDPTCOMPLETE).
Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 13-93. Interrupt Handling Order (continued)
Table 13-94. Low Frequency Interrupt Events
Change software state information.
Change software state information. Low power handling as necessary.
Change software state information. Abort pending transfers.
Handle completion of dTD as indicated in
Action as deemed necessary by application. This interrupt may not have a use in all
applications.
Table 13-95. Error Interrupt Events
Table
Action
Action
13-94. These interrupts can be handled in
Action
Section 13.8.4, “Managing Queue
Universal Serial Bus Interface
Heads”.
13-149