MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1092

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DUART
All DUART registers are one byte wide; reads and writes to these registers must be byte-wide operations.
Table 18-3
information about each register. Undefined byte address spaces within offset 0x4000–0x4FFF are
reserved.
18-4
0x0_4500
0x0_4501
0x0_4502
0x0_4503
0x0_4504
0x0_4505
0x0_4506
0x0_4507
0x0_4510
0x0_4600
0x0_4601
0x0_4602
0x0_4603
0x0_4604
0x0_4605
0x0_4606
Offset
provides a register summary with references to the section and page that contain detailed
URBR—ULCR[DLAB] = 0 UART1 receiver buffer register
UDSR—ULCR[DLAB] = x UART1 DMA status register
UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte register
UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART1 divisor most significant byte register
UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
UAFR—ULCR[DLAB] = 1 UART1 alternate function register
ULCR—ULCR[DLAB] = x UART1 line control register
UMCR—ULCR[DLAB] = x UART1 MODEM control register
ULSR—ULCR[DLAB] = x UART1 line status register
Reserved
USCR—ULCR[DLAB] = x UART1 scratch register
URBR—ULCR[DLAB] = 0 UART2 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART2 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART2 divisor least significant byte register
UIER—ULCR[DLAB] = 0 UART2 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART2 divisor most significant byte register
UIIR—ULCR[DLAB] = 0 UART2 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART2 FIFO control register
UAFR—ULCR[DLAB] = 1 UART2 alternate function register
ULCR—ULCR[DLAB] = x UART2 line control register
UMCR—ULCR[DLAB] = x UART2 MODEM control register
ULSR—ULCR[DLAB] = x UART2 line status register
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 18-3. DUART Register Summary
UART 1—Block Base Address 0x0_4000
UART 2—Block Base Address 0x0_4100
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
—
W
W
—
R
R
R
R
R
R
R
0x0000
0x0000
0x0000
0x0000
0x0000
0x0001
0x0000
0x0000
0x0000
0x0000
0x0060
0x0000
0x0001
0x0000
0x0000
0x0000
0x0000
0x0000
0x0001
0x0000
0x0000
0x0000
0x0000
0x0060
Reset
Freescale Semiconductor
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18.3.1.11/18-14
18.3.1.10/18-14
18.3.1.12/18-15
18.3.1.11/18-14
18.3.1.7/18-10
18.3.1.8/18-12
18.3.1.9/18-13
18.3.1.7/18-10
18.3.1.8/18-12
18.3.1.9/18-13
Section/Page
18.3.1.1/18-5
18.3.1.2/18-5
18.3.1.3/18-6
18.3.1.4/18-7
18.3.1.3/18-6
18.3.1.5/18-8
18.3.1.6/18-9
18.3.1.1/18-5
18.3.1.2/18-5
18.3.1.3/18-6
18.3.1.4/18-7
18.3.1.3/18-6
18.3.1.5/18-8
18.3.1.6/18-9
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