MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 27

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
ULPI Register Access (ULPI VIEWPORT) ....................................................................... 13-23
Configure Flag Register (CONFIGFLAG) ......................................................................... 13-24
Port Status and Control (PORTSC)..................................................................................... 13-25
OTG Status Control (OTGSC)............................................................................................ 13-30
USB Mode (USBMODE) ................................................................................................... 13-32
Endpoint Setup Status (ENDPTSETUPSTAT) ................................................................... 13-33
Endpoint Initialization (ENDPTPRIME) ............................................................................ 13-34
Endpoint Flush (ENDPTFLUSH) ....................................................................................... 13-35
Endpoint Status (ENDPTSTATUS)..................................................................................... 13-35
Endpoint Complete (ENDPTCOMPLETE) ........................................................................ 13-36
Endpoint Control 0 (ENDPTCTRL0) ................................................................................. 13-37
Endpoint Control 1 to 5 (ENDPTCTRLn) .......................................................................... 13-38
Snoop 1 and Snoop 2 (SNOOPn)........................................................................................ 13-40
Age Count Threshold (AGE_CNT_THRESH)................................................................... 13-41
Priority Control (PRI_CTRL) ............................................................................................. 13-42
System Interface Control Register (SI_CTRL)................................................................... 13-42
USB General-Purpose Register (CONTROL) .................................................................... 13-43
Periodic Schedule Organization.......................................................................................... 13-47
Frame List Link Pointer Format.......................................................................................... 13-47
Asynchronous Schedule Organization ................................................................................ 13-48
Isochronous Transaction Descriptor (iTD) ......................................................................... 13-49
Split-Transaction Isochronous Transaction Descriptor (siTD) ........................................... 13-52
Queue Element Transfer Descriptor (qTD)......................................................................... 13-56
Queue Head Layout ............................................................................................................ 13-62
Frame Span Traversal Node Structure ................................................................................ 13-66
Derivation of Pointer into Frame List Array....................................................................... 13-72
General Format of Asynchronous Schedule List ................................................................ 13-73
Frame Boundary Relationship Between HS Bus and FS/LS Bus ....................................... 13-73
Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries .............. 13-74
Example Periodic Schedule ................................................................................................ 13-76
Example Association of iTDs to Client Request Buffer ..................................................... 13-79
Generic Queue Head Unlink Scenario ................................................................................ 13-84
Asynchronous Schedule List with Annotation to Mark Head of List................................. 13-85
Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................... 13-87
Host Controller Asynchronous Schedule Split-Transaction State Machine ....................... 13-90
Split Transaction, Interrupt Scheduling Boundary Conditions ........................................... 13-93
General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................... 13-94
Example Host Controller Traversal of Recovery Path via FSTNs...................................... 13-96
Split Transaction State Machine for Interrupt..................................................................... 13-99
Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 13-106
siTD Scheduling Boundary Examples .............................................................................. 13-108
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
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