MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 502

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
11-22
16–23
24–27
Bit
28
SDCLKFS SD_CLK frequency select. This field, together with DVS, selects the frequency of SD_CLK pin. This
CLKEN
Name
DVS
bit holds the prescaler of the base clock frequency. Only the following settings are allowed:
0x01 Base clock divided by 2
0x02 Base clock divided by 4
0x04 Base clock divided by 8
0x08 Base clock divided by 16
0x10 Base clock divided by 32
0x20 Base clock divided by 64
0x40 Base clock divided by 128
0x80 Base clock divided by 256
Multiple bits must not be set or the behavior of this prescaler is undefined.
According to the SD Physical Specification and the SDIO Card Specification version 1.2 2.0 , the
maximum SD clock frequency is 50 MHz, and should never exceed this limit. The frequency of
SD_CLK is set by the following formula:
For example, if the base clock frequency is 96 MHz, and the target frequency is 25 MHz, then
choosing the prescaler value of 0x1 and divisor value of 0x1 yields 24 MHz, which is the nearest
frequency less than or equal to the target. Similarly, to approach a clock value of 400 KHz, the
prescaler value of 0x04 and divisor value of 0xE yields the exact clock value of 400 KHz.
The reset value of this bit field is 0x80. So, if the input base clock is about 96 MHz, the default SD
clock after reset is 375 KHz.
Note: The base clock frequency equals the csb_clk / SCCR[SDHCCM].
Divisor. Provides a more exact divisor to generate the desired SD clock frequency. The settings are
as follows:
0x0
0x1
...
0xE Divide by 15
0xF Divide by 16
SD Card Clock Enable
0 Disable the clock
1 Enable the clock
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 11-13. SYSCTL Field Descriptions (continued)
Divide by 1
Divide by 2
clock frequency = (base clock) / [(SDCLKFS
Description
×
2)
×
(DVS +1)]
Freescale Semiconductor
Eqn. 11-1