MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 467

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.5.3.5
An example of configuring FCM to execute a block erase command to large-page NAND Flash is shown
in
erase status in MDR[AS0]. The sequence is initiated by writing FMR[OP] = 11, and issuing a special
operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete interrupt
(LTESR[CC]) if interrupts are enabled.
Note that operations specified by OP3 and OP4 (status read) should never be skipped while erasing a
NAND Flash device, because, in case that happens, contention may arise on LGPL4. A possible case is
that the next transaction from eLBC may try to use that pin as an output and since the NAND Flash device
might already be driving it, contention will occur. In case OP3 and OP4 operations are skipped, it may also
happen that a new command is issued to the NAND Flash device even when the device has not yet finished
processing the previous request. This may also result in unpredictable behavior.
Freescale Semiconductor
Table
10-47. This sequence does not require use of the shared FCM buffer RAM, but returns with the
Register
Register
MDR
FBAR
FBCR
FPAR
MDR
FIR
FCR
FIR
NAND Flash Block Erase Command Sequence Example
Table 10-46. FCM Register Settings for Page Read (OR n [PGS] = 1) (continued)
Table 10-47. FCM Register Settings for Block Erase (OR n [PGS] = 1)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
(for example, block
Initial Contents
Initial Contents
0x4125E000
0x00010AB4)
0x426DB000
0x6070D000
0x00000000
block index
—
—
—
unused
OP0 = CM0 = command 0;
OP1 = CA = column address;
OP2 = PA = page address;
OP3 = CM1 = command 1;
OP4 = RBW = wait on Flash ready and read data into FCM buffer;
OP5–OP7 = NOP
CMD0 = 0x60 = block address entry;
CMD1 = 0x70 = read status
CMD2 = 0xD0 = erase block;
BLK locates index of 128-Kbyte block
PI = 0 to locate block boundary
unused
returns with AS0 holding erase status
OP0 = CM0 = command 0;
OP1 = PA = page address;
OP2 = CM2 = command 2;
OP3 = CW1 = wait on Flash ready and issue command 1;
OP4 = RS = read erase status into MDR[AS0];
OP5–OP7 = NOP
Description
Description
Enhanced Local Bus Controller
10-87