MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 328

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
1
9.4.1
This section describes the DDR memory controller registers. Shading indicates reserved fields that should
not be written.
9.4.1.1
The chip select bounds registers (CSn_BNDS) define the starting and ending address of the memory space
that corresponds to the individual chip selects. Note that the size specified in CSn_BNDS should equal the
size of physical DRAM. Also, note that EAn must be greater than or equal to SAn.
9-10
0x140–
0x150–
0xBFC
0xE4C
Offset
0x11C
0xBF4
0xBF8
0xE00
0xE04
0xE08
0xE20
0xE24
0xE28
0xE40
0xE44
0xE48
0xE50
0xE54
0xE58
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x144
0x148
Implementation-dependent reset values are listed in specified section/page.
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Reserved
DDR_INIT_ADDR—DDR training initialization address
Reserved
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
DATA_ERR_INJECT_HI—Memory data path error injection mask high
DATA_ERR_INJECT_LO—Memory data path error injection mask low
ERR_INJECT—Memory data path error injection mask ECC
CAPTURE_DATA_HI—Memory data path read capture high
CAPTURE_DATA_LO—Memory data path read capture low
CAPTURE_ECC—Memory data path read capture ECC
ERR_DETECT—Memory error detect
ERR_DISABLE—Memory error disable
ERR_INT_EN—Memory error interrupt enable
CAPTURE_ATTRIBUTES—Memory error attributes capture
CAPTURE_ADDRESS—Memory error address capture
Reserved
ERR_SBE—Single-Bit ECC memory error management
Register Descriptions
Chip Select Memory Bounds (CS n _BNDS)
Table 9-5. DDR Memory Controller Memory Map (continued)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
R
R
0x nnnn _ nnnn
0x00 nn _00 nn
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
Reset
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Freescale Semiconductor
1
1
Section/Page
9.4.1.10/9-24
9.4.1.11/9-25
9.4.1.12/9-27
9.4.1.13/9-28
9.4.1.14/9-28
9.4.1.15/9-29
9.4.1.16/9-29
9.4.1.17/9-30
9.4.1.18/9-30
9.4.1.19/9-31
9.4.1.20/9-31
9.4.1.21/9-32
9.4.1.22/9-32
9.4.1.23/9-33
9.4.1.24/9-33
9.4.1.25/9-34
9.4.1.26/9-35
9.4.1.27/9-36
9.4.1.28/9-37
9.4.1.29/9-37
9.4.1.7/9-19
9.4.1.8/9-22
9.4.1.9/9-23
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